China's RatingDog manufacturing PMI in January was 50.3, with sales prices rising for the first time in 14 months

# Source: Wall Street CN

By Zhang Yaqi

The race for TSMC’s most advanced process nodes has intensified, with the first batch of 2nm production capacity fully booked by Apple and Qualcomm. As tech giants including NVIDIA and AMD lock in subsequent nodes, the dual squeeze from AI and mobile chips has led to a severe supply shortage. Although TSMC plans to double its monthly production capacity for advanced packaging technologies such as CoWoS by 2026, supply chain tightness is expected to persist until 2027 due to yield challenges and the iteration of new technologies like backside power delivery.

The scramble for TSMC’s cutting-edge process capacity is officially underway. Global tech giants are accelerating their push into the 2nm process node, whose production capacity has been fully reserved, while the supply of advanced packaging is tightening in tandem. This underscores the persistent squeeze on the semiconductor supply chain from the combined demand for AI and mobile chips.

At a banquet for core supply chain executives on the evening of January 31, NVIDIA CEO Jensen Huang stated that TSMC must operate at full capacity this year, directly highlighting the acute shortage of advanced process production capacity. His remarks confirmed the industry’s judgment that TSMC’s 2nm capacity is in critical short supply.

Citing industry insiders, reports indicate that Apple has secured more than half of the first batch of 2nm production capacity, with Qualcomm also named a key customer for 2026. AMD plans to start manufacturing 2nm-based CPUs in 2026, while Google and AWS aim to adopt the process in the third and fourth quarters of 2027 respectively. NVIDIA is even looking ahead to 2028, with its Feynman AI GPU set to use TSMC’s A16 process, which integrates backside power delivery technology.

The tight supply situation is expected to continue until 2027. AI accelerators and mobile processors are competing for limited production capacity, and yield challenges in advanced packaging have further exacerbated the supply-demand imbalance. Institutional investors project that TSMC’s monthly CoWoS production capacity will surge by over 70% year-on-year in 2026, yet it will still fall short of market demand.

## Mobile Chips Secure First-Batch Capacity, AI Clients to Scale Up Massively in 2027

Reports show that TSMC’s 2nm and 3nm process nodes are both facing production constraints, with high-performance computing (HPC) and mobile chips vying for limited supply. Apple and Qualcomm will be the primary 2nm customers in 2026, and Wccftech cited insiders as saying Apple has secured more than half of the inaugural 2nm production capacity.

Starting in 2027, general-purpose GPUs and custom ASICs will see large-scale production ramp-up. Analysts note this will include AMD’s MI series GPUs, Google’s 8th-generation TPUs, and AWS’s Trainium 4. Industry insiders expect TSMC’s 2nm family to become a long-lifecycle node, with its initial capacity ramp likely to take longer than that of the 3nm generation.

The N2 process will enter mass production in 2026, followed by the N2P and A16 processes in the second half of the year. Among them, the A16 process is tailored for high-performance computing products requiring complex wiring and high-density power delivery.

## NVIDIA Skips 2nm for 1.6nm, Betting Big on Backside Power Delivery Technology

NVIDIA’s process roadmap reveals a distinct strategy. Reports state the company plans to launch its Feynman AI GPU in 2028, which is expected to adopt TSMC’s A16 process featuring backside power delivery technology.

The A16 process represents TSMC’s 1.6nm node, exclusively designed for high-performance computing products. Backside power delivery technology moves the power distribution network to the back of the chip, improving signal integrity and power transmission efficiency—an especially critical feature for large AI accelerators.

This timeline suggests NVIDIA may skip or only adopt the 2nm process on a small scale, moving directly to a more advanced node, reflecting the aggressive pursuit of process technology by AI chip manufacturers.

## Advanced Packaging Emerges as a New Bottleneck, CoWoS Capacity Growth Fails to Keep Pace with Demand

Capacity shortages are not limited to the wafer foundry segment. Reports point out that TSMC is upgrading its advanced packaging ecosystem. As AI chips fully enter the era of chiplet architectures and ultra-large packaging sizes, single-chip designs can no longer meet computing power demands, making technologies such as CoWoS-L, SoIC and hybrid bonding de facto standard configurations.

Citing institutional investors, reports note TSMC targets a year-on-year increase of over 70% in monthly CoWoS production capacity by 2026, while gradually validating next-generation technologies such as CoWoP (Chip-on-Wafer-on-PCB) and CPO (Co-packaged Optics).

Yet the supply-demand imbalance remains a key bottleneck. In addition to the tight 2nm foundry capacity, improving yields for large-scale system-in-package (SiP) is another major challenge. As the packaging size of AI chips continues to expand, the difficulty of maintaining high yields rises significantly, which may further constrain the supply capacity of advanced chips.

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